Semiconductor package

ABSTRACT

A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.

CROSS REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2021-0134436, filed on Oct. 8, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

Embodiments relate to a semiconductor package. In particular, embodiments relate to a semiconductor package including a passive element and a semiconductor chip.

2. Description of the Related Art

A solder paste may be used when a passive element is mounted on a package substrate. A passive element connecting member between the package substrate and the passive element and a flux layer on the package substrate may be made from the solder paste.

SUMMARY

According to an aspect of embodiments, there is provided a semiconductor package that may include a package substrate having a passive element region, a passive element adjacent region adjacent to the passive element region, and a remaining region; a first passive element on an upper surface of the passive element region; a first semiconductor chip on an upper surface of the remaining region; and a sealing portion covering the package substrate, the first passive element, and the first semiconductor chip, wherein the passive element adjacent region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side of the first passive element, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side of the first passive element, and a roughness of an upper surface of at least one of the first sub-region to the fourth sub-region is greater than the roughness of an upper surface of the remaining region.

According to another aspect of embodiments, there is provided a semiconductor package that may include a package substrate having a wire pad, a wire pad, a wire pad adjacent region adjacent to the wire pad, and a remaining region; a passive element on an upper surface of the remaining region; a semiconductor chip on the upper surface of the remaining region; a wire electrically connecting the semiconductor chip to the wire pad; and a sealing portion covering the package substrate, the passive element, the semiconductor chip, and the wire, wherein the roughness of an upper surface of the wire pad adjacent region is less than the roughness of the upper surface of the remaining region.

According to another aspect of embodiments, there is provided a semiconductor package that may include a package substrate having a passive element region, a passive element adjacent region adjacent to the passive element region, and a remaining region; a plurality of external connection terminals on a lower surface of the package substrate; a passive element on an upper surface of the passive element region; a memory controller chip on the upper surface of the remaining region; a chip bump connecting the memory controller chip to the package substrate; a memory chip on the memory controller chip or the remaining region; a wire connecting the memory chip to the package substrate; and a sealing portion covering the package substrate, the passive element, the memory controller chip, the chip bump, the memory chip, and the wire, wherein the passive element adjacent region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side of the first passive element, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side of the first passive element, and the roughness of the upper surface of at least one of the first sub-region to the fourth sub-region is greater than the roughness of the upper surface of the remaining region.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

FIG. 1A is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 1B is an enlarged view of region B in FIG. 1A;

FIG. 1C is a plan view of a semiconductor package according to an embodiment;

FIG. 2 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 3 is a plan view of a semiconductor package according to an embodiment;

FIG. 4 is a plan view of a semiconductor package according to an embodiment;

FIG. 5 is a plan view of a semiconductor package according to an embodiment;

FIG. 6 is a plan view of a semiconductor package according to an embodiment;

FIG. 7 is a plan view of a semiconductor package according to an embodiment;

FIG. 8 is a plan view of a semiconductor package according to an embodiment;

FIG. 9 is a plan view of a semiconductor package according to one embodiment;

FIG. 10 is a plan view of a semiconductor package according to an embodiment;

FIG. 11 is a plan view of a semiconductor package according to an embodiment;

FIG. 12 is a plan view of a semiconductor package according to an embodiment;

FIG. 13 is a plan view of a semiconductor package according to an embodiment;

FIG. 14 is a plan view of a semiconductor package according to an embodiment;

FIG. 15 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 16 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 17 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 18 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 19 is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 20A is a cross-sectional view of a semiconductor package according to an embodiment;

FIG. 20B is an enlarged view of region B2 in FIG. 20A; and

FIG. 21 is a flowchart of a method of manufacturing a semiconductor package, according to an embodiment.

DETAILED DESCRIPTION

FIG. 1A is a cross-sectional view showing a semiconductor package 1000 according to an embodiment. FIG. 1B is an enlarged view of region B in FIG. 1A, and FIG. 1C is a plan view showing the semiconductor package 1000 according to an embodiment.

Referring to FIGS. 1A to 1C, the semiconductor package 1000 may include a package substrate 100, a plurality of external connection terminals 500 on a lower surface of the package substrate 100, a passive element 200 on an upper surface of the package substrate 100, a plurality of passive element connecting members 250 for connecting the passive element 200 to the package substrate 100, a semiconductor chip 300 on the upper surface of the package substrate 100, a plurality of chip bumps 350 connecting the semiconductor chip 300 to the package substrate 100, and a sealing portion 400 covering the semiconductor chip 300. In some embodiments, the semiconductor package 1000 may further include a flux layer 270 on the package substrate 100.

The package substrate 100 may include a printed circuit board (PCB). For example, the package substrate 100 may include a core layer 111, a first insulating layer 121 a on an upper surface of the core layer 111, a second insulating layer 121 b on a lower surface of the core layer 111, a third insulating layer 121 c on the upper surface of the first insulating layer 121 a, a fourth insulating layer 121 d on the lower surface of the second insulating layer 121 b, a fifth insulating layer 121 e on the upper surface of the third insulating layer 121 c, and a sixth insulating layer 121 f on the lower surface of the fourth insulating layer 121 d. The package substrate 100 may further include a first protective layer 130 on an upper surface of the fifth insulating layer 121 e and a second protective layer 140 on a lower surface of the sixth insulating layer 121 f.

The package substrate 100 may further include a core via 113 penetrating the core layer 111. The package substrate 100 may further include a first core wiring layer 112 a positioned on the upper surface of the core layer 111 and in contact with the core via 113. The package substrate 100 may further include a second core wiring layer 112 b positioned on the lower surface of the core layer 111 and in contact with the core via 113.

The package substrate 100 may further include a first wiring layer 122 a on the upper surface of the first insulating layer 121 a. The package substrate 100 may further include a first via layer 123 a passing through the first insulating layer 121 a between the first wiring layer 122 a and the first core wiring layer 112 a. The package substrate 100 may further include a second wiring layer 122 b on a lower surface of the second insulating layer 121 b. The package substrate 100 may further include a second via layer 123 b passing through the second insulating layer 121 b between the second wiring layer 122 b and the second core wiring layer 112 b. The package substrate 100 may further include a third wiring layer 122 c on the upper surface of the third insulating layer 121 c. The package substrate 100 may further include a third via layer 123 c passing through the third insulating layer 121 c between the third wiring layer 122 c and the first wiring layer 122 a. The package substrate 100 may further include a fourth wiring layer 122 d on the lower surface of the fourth insulating layer 121 d. The package substrate 100 may further include a fourth via layer 123 d passing through the fourth insulating layer 121 d between the fourth wiring layer 122 d and the second wiring layer 122 b.

The package substrate 100 may further include a plurality of bump pads 124 a-1 and a plurality of passive element pads 124 a-2 on the upper surface of the fifth insulating layer 121 e. The first protective layer 130 may have a plurality of openings exposing the plurality of bump pads 124 a-1 and the plurality of passive element pads 124 a-2, respectively. The package substrate 100 may further include a fifth via layer 123 e passing through the fifth insulating layer 121 e between the third wiring layer 122 c and the plurality of bump pads 124 a-1 and between the third wiring layer 122 c and the plurality of passive element pads 124 a-2. The package substrate 100 may further include a plurality of external connection terminal pads 124 b on the lower surface of the sixth insulating layer 121 f. The second protective layer 140 may have a plurality of openings exposing the plurality of external connection terminal pads 124 b. The package substrate 100 may further include a sixth via layer 123 f passing through the sixth insulating layer 121 f between the fourth wiring layer 122 d and the plurality of external connection terminal pads 124 b.

In FIG. 1A, the package substrate 100 includes six insulating layers (i.e., the first to sixth insulating layers 121 a to 121 f), four wiring layers (i.e., the first to fourth wiring layers 122 a to 122 d), and six via layers (i.e., the first to sixth via layers 123 a to 123 f). However, the numbers of insulating layers, wiring layers, and via layers included in the package substrate 100 may be variously modified.

For example, the core layer 111 may include an insulating material, a thermosetting resin (e.g., an epoxy resin) or a thermoplastic resin (e.g., polyimide). The core layer 111 may include a material including a reinforcing material, e.g., fiberglass, and/or an inorganic filler, e.g., a copper clad laminate (CCL) or an unclad CCL. The core layer 111 may include a metal plate, a glass plate, or a ceramic plate.

The first to sixth insulating layers 121 a to 121 f may include a thermosetting resin, e.g., epoxy, or a thermoplastic resin, e.g., polyimide. In some embodiments, the first to sixth insulating layers 121 a to 121 f may include a material including a reinforcing material, e.g., glass fiber, and/or an inorganic filler in addition to a thermoplastic resin and/or a thermosetting resin, e.g., prepreg or Ajinomoto build-up film (ABF). In some embodiments, the first protective layer 130 and the second protective layer 140 may include solder resist.

The core via 113, the first and second core wiring layers 112 a and 112 b, the first to fourth wiring layers 122 a to 122 d, the first to sixth via layers 123 a to 123 f, the bump pads 124 a-1, the passive element pads 124 a-2, and the external connection terminal pads 124 b may include a metal material. The metal material may include, e.g., copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

As shown in FIG. 1C, the package substrate 100 may have a passive element region R1, a passive element adjacent region R2 adjacent to the passive element region R1, and a remaining region R3. For example, the passive element adjacent region R2 may be a peripheral region of the passive element region R1. In some embodiments, the passive element adjacent region R2 may surround, e.g., an entire perimeter of, the passive element region R1, and the remaining region R3 may surround, e.g., an entire perimeter of, the passive element adjacent region R2, as viewed in a top view (FIG. 1C).

The plurality of external connection terminals 500 may be respectively positioned on the plurality of external connection terminal pads 124 b of the package substrate 100. Each of the external connection terminals 500 may include, e.g., tin (Sn) or a tin (Sn) alloy. In some embodiments, each external connection terminal 500 may be formed of a solder ball.

The passive element 200 may be located on the passive element region R1. The passive element 200 may be positioned on the plurality of passive element pads 124 a-2 of the package substrate 100. The passive element 200 may be, e.g., a capacitor, an inductor, or a resistor.

The plurality of passive element connecting members 250 may be located between the passive element region R1 of the package substrate 100 and the passive element 200, e.g., the plurality of passive element connecting members 250 may be between the package substrate 100 and the passive element 200 along the Z direction. The plurality of passive element connecting members 250 may be located between the passive element 200 and the plurality of passive element pads 124 a-2, respectively. The plurality of passive element connecting members 250 may include, e.g., tin (Sn) or tin (Sn) alloys. In some embodiments, a plurality of passive element connecting members 250 may be formed of a solder paste.

The semiconductor chip 300 may be located on the remaining region R3. The semiconductor chip 300 may be located on the plurality of bump pads 124 a-1 of the package substrate 100. The semiconductor chip 300 may include an arbitrary kind of integrated circuit including, e.g., a memory circuit, a logic circuit, or a combination thereof. The memory circuit may be, e.g., a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a flash memory circuit, an electrically erasable and programmable read-only memory (EEPROM) circuit, a phase-change random access memory (PRAM) circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (RRAM) circuit, or a combination thereof. The logic circuit may be, e.g., a central processing unit (CPU) circuit, a graphics processing unit (GPU) circuit, a memory controller circuit, an application specific integrated circuit (ASIC) circuit, an application processor (AP) circuit, or a combination thereof.

The chip bumps 350 may be located between the remaining region R3 of the package substrate 100 and the semiconductor chip 300, e.g., the chip bumps 350 may be between the package substrate 100 and the semiconductor chip 300 along the Z direction. The chip bumps 350 may be located between the semiconductor chip 300 and the plurality of bump pads 124 a-1, respectively. The chip bumps 350 may include, e.g., a tin (Sn) or a tin (Sn) alloy. In some embodiments, the chip bump 350 may be formed of a solder ball.

The sealing portion 400 may cover the package substrate 100, the passive element 200, and the semiconductor chip 300. The sealing portion 400 may include an epoxy resin. For example, the sealing portion 400 may include an epoxy mold compound (EMC).

The flux layer 270 may be located on the passive element adjacent region R2. In some embodiments, the flux layer 270 may be further positioned on the passive element region R1. In some embodiments, the flux layer 270 may be formed of flux of solder paste.

Referring to FIG. 1C, the passive element adjacent region R2 may include a first sub-region R2 a on the first side of the passive element 200, a second sub-region R2 b on a second side opposite to the first side of the passive element 200, a third sub-region R2 c on a third side of the passive element 200, and a fourth sub-region R2 d of a fourth side opposite to the third side of the passive element 200. In some embodiments, the passive element adjacent region R2 may further include a fifth sub-region R2 e in which the first sub-region R2 a intersects with the third sub-region R2 c, a sixth sub-region R2 f in which the first sub-region R2 a intersects with the fourth sub-region R2 d, a seventh sub-region R2 g in which the third sub-region R2 c intersects with the second sub-region R2 b, and an eighth sub-region R2 h in which the fourth sub-region R2 d intersects with the second sub-region R2 b. In some embodiments, e.g., each of, the width Wa of the first sub-region R2 a, the width Wb of the second sub-region R2 b, the width Wc of the third sub-region R2 c, and the width Wd of the fourth sub-region R2 d may be about 10 µm to about 500 µm.

In some embodiments, the roughness of the upper surface of the first sub-region R2 a to the fourth sub-region R2 d may be greater than the roughness of the upper surface of the remaining region R3. For example, referring to FIG. 1B, the roughness of the upper surface, i.e., a surface facing the passive element 200, of the first sub-region R2 a to the fourth sub-region R2 d may be greater than the roughness of the upper surface, i.e., a surface facing the semiconductor chip 300, of the remaining region R3.

In this specification, roughness means average roughness (roughness average, Ra). In some embodiments, the roughness of the upper surface of the first sub-region R2 a to the fourth sub-region R2 d may be greater than the roughness of the upper surface of the remaining region R3 by about 80 nm or more. In some embodiments, the roughness of the upper surface of the fifth sub-region R2 e to the eighth sub-region R2 h may be greater than the roughness of the upper surface of the remaining region R3. In some embodiments, the roughness of the upper surface of the fifth sub-region R2 e to the eighth sub-region R2 h may be greater than the roughness of the upper surface of the remaining region R3 by about 80 nm or more.

The greater the roughness of the surface through which the flux flows, the wider the flux may flow. Because the passive element adjacent region R2 has a rough surface, the flux layer 270 may be formed wider on the passive element adjacent region R2. Accordingly, the concentration of the flux mixed in the sealing portion 400 may be reduced. Therefore, the possibility of delamination caused by combining the sealing portion 400 with the flux layer 270 may be reduced. On the other hand, by forming the remaining region R3 to be relatively flat, i.e., a lower surface roughness, the flow of the flux layer 270 to the remaining region R3 may be reduced. Therefore, the flux layer 270 may be prevented from contaminating the bump pads 124 a-1 located in the remaining region R3.

In some embodiments, the roughness of the upper surface of the passive element region R1 may be greater than the roughness of the upper surface of the remaining region R3. For example, the roughness of the upper surface of the passive element region R1 may be greater than the roughness of the upper surface of the remaining region R3 by about 80 nm or more.

FIG. 2 is a cross-sectional view showing a semiconductor package 1000 a according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 a shown in FIG. 2 are described.

Referring to FIG. 2 , the roughness of the upper surface of the passive element region R1 may be less than the roughness of the upper surface of the passive element adjacent region R2. For example, the roughness of the upper surface of the passive element region R1 may be less than the roughness of the upper surface of the first sub-region R2 a. For example, the roughness of the upper surface of the passive element region R1 may be less than the roughness of the upper surface of the passive element adjacent region R2 by about 80 nm or more. The roughness of the upper surface of the passive element region R1 may be less than the roughness of the upper surface of the second to fourth sub regions (refer to R2 b to R2 d, and FIG. 1C). For example, the roughness of the upper surface of the passive element region R1 may be less than the roughness of the upper surface of the upper surface of the second to fourth sub regions R2 b to R2 d (refer to FIG. 1C) by about 80 nm or more.

FIG. 3 is a plan view showing a semiconductor package 1000 b according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 b shown in FIG. 3 are described.

Referring to FIG. 3 , the roughness of an upper surface of a first sub-region R2 a-1 may be less than the roughness of an upper surface of a second sub-region R2 b to a fourth sub-region R2 d. For example, the roughness of the upper surface of the first sub-region R2 a-1 may be less than the roughness of the upper surface of the second sub-region R2 b to the fourth sub-region R2 d by 80 nm or more.

In some embodiments, the roughness of upper surfaces of a fifth sub-region R2 e-1 and a sixth sub-region R2 f-1 may be less than roughness of the upper surfaces of a seventh sub-region R2 g and an eighth sub-region R2 h. For example, the roughness of the upper surface of the fifth sub-region R2 e-1 and the sixth sub-region R2 f-1 may be less than the roughness of the upper surface of the seventh sub-region R2 g and the eighth sub-region R2 h by 80 nm or more

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 to be relatively flat, the flow of the flux layer 270 to the first side of the passive element 200 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the semiconductor chip 300 positioned on the first side of the passive element 200.

FIG. 4 is a plan view showing a semiconductor package 1000 c according to an embodiment. Hereinafter, differences between the semiconductor packages 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 c shown in FIG. 4 are described.

Referring to FIG. 4 , the semiconductor package 1000 c may include the package substrate 100, a first passive element 201, a first passive element connecting member 251, a first flux layer 271, a second passive element 202, a second passive element connecting member 252, a second flux layer 272, and the semiconductor chip 300. The package substrate 100 may include a first passive element region R1 a, a first passive element adjacent region R2 adjacent to the first passive element region R1 a, a second passive element region R1 b positioned on the first side of the first passive element region R1 a, a second passive element adjacent region R4 adjacent to the second passive element region R1 b, and a remaining region R3. The first passive element 201 may be located on the first passive element region R1 a, and the second passive element 202 may be located on the second passive element region R1 b, and the semiconductor chip 300 may be located on the remaining region R3. A plurality of first passive element connecting members 251 may connect the first passive element 201 to the package substrate 100, and a plurality of second passive element connecting members 252 may connect the second passive element 202 to the package substrate 100. The first flux layer 271 may be located on the first passive element region R1 a and the first passive element adjacent region R2, and the second flux layer 272 may be located on the second passive element region R1 b and the second passive element adjacent region R4.

The first passive element adjacent region R2 may include a first sub-region R2 a-1 on a first side of the first passive element 201, a second sub-region R2 b on a second side opposite to the first side of the first passive element 201, a third sub-region R2 c on a third side of the first passive element 201, and the fourth sub-region R2 d on a fourth side opposite to the third side of the first passive element 201. In some embodiments, the first passive element adjacent region R2 may further include a fifth sub-region R2 e-1 in which the first sub-region R2 a-1 intersects with the third sub-region R2 c, a sixth sub-region R2 f-1 in which the first sub-region R2 a-1 intersects with the fourth sub-region R2 d, a seventh sub-region R2 g in which the third sub-region R2 c intersects with the second sub-region R2 b, and an eighth sub-region R2 h in which the fourth sub-region R2 d intersects with the second sub-region R2 b.

The second passive element 202 may be located on the first side of the first passive element 201, e.g., the second passive element 202 may be between the first passive element 201 and the semiconductor chip 300 along the X direction. In this case, the roughness of the upper surface of the first sub-region R2 a-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surfaces of the second sub-region R2 b to the fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of the upper surface of the first sub-region R2 a-1 of the first passive element adjacent region R2 may be less than that of the upper surface of the second sub-region R2 b to the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

The roughness of the upper surfaces of the fifth sub-region R2 e-1 and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surfaces of the seventh sub-region R2 g and the eighth sub-region R2 h of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the fifth sub-region R2 e-1 and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the seventh sub-region R2 g and the eighth sub-region R2 h of the first passive element adjacent region R2 by 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the second flux layer 272. Therefore, it is possible to prevent an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A). Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

The second passive element adjacent region R4 may include a first sub-region R4 a-1 on a first side of the second passive element 202, a second sub-region R4 b-1 on a second side opposite to the first side of the second passive element 202, a third sub-region R4 c on a third side of the second passive element 202, and a fourth sub-region R4 d on a fourth side opposite to the third side of the second passive element 202. In some embodiments, the second passive element adjacent region R4 may further include a fifth sub-region R4 e-1 in which the first sub-region R4 a-1 intersects with the third sub-region R4 c, a sixth sub-region R4 f-1 in which the first sub-region R4 a-1 intersects with the fourth sub-region R4 d, a seventh sub-region R4 g-1 in which the third sub-region R4 c intersects with the second sub-region R4 b-1, and an eighth sub-region R4 h-1 in which the fourth sub-region R4 d intersects with the second sub-region R4 b-1.

The first passive element 201 may be positioned on the second side of the second passive element 202, and the semiconductor chip 300 may be positioned on the first side of the second passive element 202. In this case, the roughness of the upper surfaces of the first sub-region R4 a-1 and the second sub-region R4 b-1 of the second passive element adjacent region R4 may be less than the roughness of the upper surfaces of the third sub-region R4 c and the fourth sub-region R4 d of the second passive element adjacent region R4. For example, the roughness of upper surfaces of the first sub-region R4 a-1 and the second sub-region R4 b-1 of the second passive element adjacent region R4 may be less than the roughness of the upper surfaces of the third sub-region R4 c and the fourth sub-region R4 d of the second passive element adjacent region R4 by 80 nm or more.

The roughness of upper surfaces of the fifth sub-region R4 e-1 to the eighth sub-region R4 h-1 of the second passive element adjacent region R4 may be less than the roughness of the upper surfaces of the third sub-region R4 c and the fourth sub-region R4 d of the second passive element adjacent region R4. For example, the roughness of upper surfaces of the fifth sub-region R4 e-1 to the eighth sub-region R4 h-1 of the second passive element adjacent region R4 may less than the roughness of the upper surfaces of the third sub-region R4 c and the fourth sub-region R4 d of the second passive element adjacent region R4 by 80 nm or more.

By forming the first sub-region R4 a-1, the fifth sub-region R4 e-1, and the sixth sub-region R4 f-1 of the second passive element adjacent region R4 to be relatively flat, the flow of the second flux layer 272 to the first side of the second passive element 202 may be reduced. Accordingly, the second flux layer 272 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the semiconductor chip 300 positioned on the first side of the second passive element 202.

By forming the second sub-region R4 b-1, the seventh sub-region R4 g-1, and the eighth sub-region R4 h-1 of the second passive element adjacent region R4 to be relatively flat, the flow of the second flux layer 272 to the second side of the second passive element 202 may be reduced. Accordingly, the second flux layer 272 may be prevented from meeting, e.g., contacting, the first flux layer 271. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 5 is a plan view showing a semiconductor package 1000 d according to an embodiment. Hereinafter, differences between the semiconductor package 1000 c shown in FIG. 4 and the semiconductor package 1000 d shown in FIG. 5 are described.

Referring to FIG. 5 , the semiconductor chip 300 may be positioned on a third side of the first passive element 201, e.g., the semiconductor chip 300 and the first passive element 201 may be adjacent to each other along the Y direction, and the second passive element 202 may be positioned on a first side of the first passive element 201, e.g., the first and second passive elements 201 and 202 may adjacent to each other along the X direction. In other words, the semiconductor chip 300 and the second passive element 202 may be positioned on adjacent (rather than opposite) sides of the first passive element 201. In this case, the roughness of upper surfaces of a first sub-region R2 a-1 and a third sub-region R2 c-1 of a first passive element adjacent region R2 may be less than the roughness of upper surfaces of a second sub-region R2 b and a fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the first sub-region R2 a-1 and the third sub-region R2 c-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the second sub-region R2 b and the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

In some embodiments, the roughness of upper surfaces of a fifth sub-region Re-1 to a seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of an eighth sub-region R2 h of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the fifth sub-region Re-1 to the seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of the eighth sub-region R2 h of the first passive element adjacent region R2 by 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming the third sub-region R2 c-1, the fifth sub-region R2 e-1, and the seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the semiconductor chip 300 positioned on the third side of the first passive element 201.

The first passive element 201 may be located on a second side of the second passive element 202. In this case, the roughness of the upper surface of the second sub-region R4 b-1 of the second passive element adjacent region R4 may be less than the roughness of upper surfaces of the first sub-region R4 a, the third sub-region R4 c, and the fourth sub-region R4 d. For example, the roughness of the upper surface of the second sub-region R4 b-1 of the second passive element adjacent region R4 may be less than the roughness of upper surfaces of the first sub-region R4 a, the third sub-region R4 c, and the fourth sub-region R4 d by about 80 nm or more.

In some embodiments, the roughness of upper surfaces of a seventh sub-region R4 g-1 and an eighth sub-region R4 h-1 of the second passive element adjacent region R4 may be less than the roughness of upper surfaces of a fifth sub-region R4 e and a sixth sub-region R4 f of the second passive element adjacent region R4. For example, the roughness of upper surfaces of the seventh sub-region R4 g-1 and the eighth sub-region R4 h-1 of the second passive element adjacent region R4 may be less than the roughness of upper surfaces of the fifth sub-region R4 e and the sixth sub-region R4 f of the second passive element adjacent region R4 by about 80 nm or more.

By forming the second sub-region R4 b-1, the seventh sub-region R4 g-1, and the eighth sub-region R4 h-1 of the second passive element adjacent region R4 to be relatively flat, the flow of the second flux layer 272 to the second side of the second passive element 202 may be reduced. Accordingly, the second flux layer 272 may be prevented from meeting, e.g., contacting, the first flux layer 271. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 6 is a plan view showing a semiconductor package 1000 e according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 e shown in FIG. 6 are described.

Referring to FIG. 6 , the semiconductor package 1000 e may include a first semiconductor chip 301 and a second semiconductor chip 302 on the remaining region R3 of the package substrate 100 (instead of the single semiconductor chip 300 illustrated in FIGS. 1A to 1C). The first semiconductor chip 301 may be located on a first side of a passive element 200, and the second semiconductor chip 302 may be located on a third side of the passive element 200.

In this case, the roughness of upper surfaces of a first sub-region R2 a-1 and a third sub-region R2 c-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of a second sub-region R2 b and a fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the first sub-region R2 a-1 and the third sub-region R2 c-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the second sub-region R2 b and the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

In some embodiments, the roughness of upper surfaces of a fifth sub-region R2 e-1 to a seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of an eighth sub-region R2 h of the first passive element adjacent region R2. For example, the roughness of the upper surfaces of the fifth sub-region R2 e-1 to the seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of the eighth sub-region R2 h of the first passive element adjacent region R2 by 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to a first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the first semiconductor chip 301 positioned on the first side of the first passive element 201.

By forming the third sub-region R2 c-1, the fifth sub-region R2 e-1, and the seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the second semiconductor chip 302 positioned on a third side of the first passive element 201.

FIG. 7 is a plan view showing a semiconductor package 1000 f according to an embodiment. Hereinafter, differences between the semiconductor package 1000 d shown in FIG. 5 and the semiconductor package 1000 f shown in FIG. 7 are described.

Referring to FIG. 7 , the semiconductor package 1000 f may further include a third passive element 203, a third passive element connecting member 253 connecting the third passive element 203 to the package substrate 100, and a third flux layer 273 adjacent to the third passive element 203 on the package substrate 100.

The second passive element 202 may be located on the first side of the first passive element 201, and the third passive element 203 may be located on the third side of the first passive element 201. In this case, the roughness of the upper surfaces of a first sub-region R2 a-1 and a third sub-region R2 c-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of a second sub-region R2 b and a fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the first sub-region R2 a-1 and the third sub-region R2 c-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the second sub-region R2 b and the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

In some embodiments, the roughness of upper surfaces of a fifth sub-region Re-1 to a seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of an eighth sub-region R2 h of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the fifth sub-region Re-1 to the seventh sub-region R2 g-1 of the first passive element adjacent region R2 may be less than the roughness of the upper surface of the eighth sub-region R2 h of the first passive element adjacent region R2 by 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201, e.g., along the X direction, may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming the third sub-region R2 c-1, the fifth sub-region R2 e-1, and the seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the third side of the first passive element 201, e.g., along the Y direction, may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the third flux layer 273. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 8 is a plan view showing a semiconductor package 1000 g according to an embodiment. Hereinafter, differences between the semiconductor package 1000 c shown in FIG. 4 and the semiconductor package 1000 g shown in FIG. 8 are described.

Referring to FIG. 8 , the second passive element 202 may be positioned on the second side of the first passive element 201, and the semiconductor chip 300 may be positioned on the first side of the first passive element 201. In this case, the roughness of upper surfaces of a first sub-region R2 a-1 and a second sub-region R2 b-1 of a first passive element adjacent region R2 may be less than the roughness of upper surfaces of a third sub-region R2 c and a fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the first sub-region R2 a-1 and the second sub-region R2 b-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the third sub-region R2 c and the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

The roughness of upper surfaces of a fifth sub-region R2 e-1 to an eighth sub-region R2 h-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of a third sub-region R2 c and a fourth sub-region R2 d of the first passive element adjacent region R2. For example, the roughness of upper surfaces of the fifth sub-region R2 e-1 to the eighth sub-region R2 h-1 of the first passive element adjacent region R2 may be less than the roughness of upper surfaces of the third sub-region R2 c and the fourth sub-region R2 d of the first passive element adjacent region R2 by 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the semiconductor chip 300 positioned on the first side of the first passive element 201.

By forming the second sub-region R2 b-1, the seventh sub-region R2 g-1, and the eighth sub-region R2 h-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the second side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion may be prevented (see 400, FIG. 1A). Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented.

FIG. 9 is a plan view showing a semiconductor package 1000 h according to an embodiment. Hereinafter, differences between the semiconductor package 1000 g shown in FIG. 8 and the semiconductor package 1000 h shown in FIG. 9 are described.

Referring to FIG. 9 , the semiconductor package 1000 h may include the passive element 200, the first semiconductor chip 301, and the second semiconductor chip 302, instead of the first passive element 201, the second passive element 202, and the semiconductor chip 300. The first semiconductor chip 301 may be located on a second side of the passive element 200, and the second semiconductor chip 302 may be located on a first side of the passive element 200. In other words, the passive element 200 may be between the first and second semiconductor chips 301 and 302 along the X direction.

By forming a first sub-region R2 a-1, a fifth sub-region R2 e-1, and a sixth sub-region R2 f-1 of a passive element adjacent region R2 relatively flat, the flow of the flux layer 270 to the first side of the passive element 200 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the second semiconductor chip 302 positioned on the first side of the passive element 200.

By forming a second sub-region R2 b-1, a seventh sub-region R2 g-1, and an eighth sub-region R2 h-1 of the passive element adjacent region R2 to be relatively flat, the flow of the flux layer 270 to the second side of the passive element 200 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the first semiconductor chip 301 positioned on the second side of the passive element 200.

FIG. 10 is a plan view showing a semiconductor package 1000 i according to an embodiment. Hereinafter, differences between the semiconductor package 1000 g shown in FIG. 8 and the semiconductor package 1000 i shown in FIG. 10 are described.

Referring to FIG. 10 , the semiconductor package 1000 i may further include the third passive element 203 on the package substrate 100, the third passive element connecting member 253 connecting the third passive element 203 to the package substrate 100, and the third flux layer 273 adjacent to the third passive element 203 on the package substrate 100. The second passive element 202 may be positioned on the second side of the first passive element 201, and the third passive element 203 may be positioned on the first side of the first passive element 201.

By forming a first sub-region R2 a-1, the fifth sub-region R2 e-1, and a sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the third flux layer 273. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming a second sub-region R2 b-1, a seventh sub-region R2 g-1, and an eighth sub-region R2 h-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the second side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting, e.g., contacting, the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 11 is a plan view showing a semiconductor package 1000 j according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 j shown in FIG. 11 are described.

Referring to FIG. 11 , the semiconductor package 1000 j may include the first semiconductor chip 301, the second semiconductor chip 302, and a third semiconductor chip 303 (instead of the single semiconductor chip 300 in FIGS. 1A-1C). The first semiconductor chip 301 may be located on the second side of a passive element 200, the second semiconductor chip 302 may be located on the first side of the passive element 200, and the third semiconductor chip 303 may be located on the third side of the passive element 200.

In this case, the roughness of top surfaces of a first sub-region R2 a-1 to a third sub-region R2 c-1 of the passive element adjacent region R2 may be less than the roughness of the upper surface of a fourth sub-region R2 d of the passive element adjacent region R2. For example, the roughness of upper surfaces of the first sub-region R2 a-1 to the third sub-region R2 c-1 of the passive element adjacent region R2 may be less than the roughness of the upper surface of the fourth sub-region R2 d of the passive element adjacent region R2 by about 80 nm or more.

The roughness of the upper surfaces of a fifth sub-region R2 e-1 to an eighth sub-region R2 h-1 of the passive element adjacent region R2 may be less than the roughness of the upper surface of a fourth sub-region R2 d of the passive element adjacent region R2. For example, the roughness of the upper surfaces of the fifth sub-region R2 e-1 to the eighth sub-region R2 h-1 of the passive element adjacent region R2 may be less than the roughness of the upper surface of the fourth sub-region R2 d of the passive element adjacent region R2 by about 80 nm or more.

By forming the first sub-region R2 a-1, the fifth sub-region R2 e-1, and the sixth sub-region R2 f-1 of the passive element adjacent region R2 relatively flat, the flow of the flux layer 270 to the first side of the passive element 200 may be reduced. Therefore, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the second semiconductor chip 302 positioned on the first side of the passive element 200.

By forming the second sub-region R2 b-1, the seventh sub-region R2 g-1, and the eighth sub-region R2 h-1 of the passive element adjacent region R2 to be relatively flat, the flow of the flux layer 270 to the second side of the passive element 200 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the first semiconductor chip 301 positioned on the second side of the passive element 200.

By forming the third sub-region R2 c-1, the fifth sub-region R2 e-1, and the seventh sub-region R2 g-1 of the passive element adjacent region R2 to be relatively flat, the flow of the flux layer 270 to the third side of the passive element 200 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the third semiconductor chip 303 positioned on the third side of the passive element 200.

FIG. 12 is a plan view showing a semiconductor package 1000 k according to an embodiment. Hereinafter, differences between the semiconductor package 1000 j shown in FIG. 11 and the semiconductor package 1000 k shown in FIG. 12 are described.

Referring to FIG. 12 , the semiconductor package 1000 k may include the first passive element 201 and the second passive element 202 on the package substrate 100 (instead of the single passive element 200 and the third semiconductor chip 303 in FIG. 11 ). The semiconductor package 1000 k may further include the second passive element connecting member 252 that connects the second passive element 202 to the package substrate 100 and the second flux layer 272 adjacent the second passive element 202 on the package substrate 100.

By forming a first sub-region R2 a-1, a fifth sub-region R2 e-1, and a sixth sub-region R2 f-1 of a first passive element adjacent region R2 relatively flat, the flow of a first flux layer 271 to a first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from contaminating the bump pads 124 a-1 (refer to FIG. 1A) under the second semiconductor chip 302 positioned on the first side of the first passive element 201.

By forming a second sub-region R2 b-1, a seventh sub-region R2 g-1, and an eighth sub-region R2 h-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to a second side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the first semiconductor chip 301 positioned on the second side of the first passive element 201.

By forming a third sub-region R2 c-1, the fifth sub-region R2 e-1, and a seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the third side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 13 is a plan view showing a semiconductor package 1000 l according to an embodiment. Hereinafter, differences between the semiconductor package 1000 k shown in FIG. 12 and the semiconductor package 1000 l shown in FIG. 13 are described.

Referring to FIG. 13 , the semiconductor package 1000 l may include the third passive element 203 and a single semiconductor chip 300 (instead of the first semiconductor chip 301 and the second semiconductor chip 302 in FIG. 12 ). The semiconductor package 1000 l may further include the third passive element connecting member 253 connecting the third passive element 203 to the package substrate 100 and the third flux layer 273 adjacent to the third passive element 203 on the package substrate 100. The second passive element 202 may be located on the second side of the first passive element 201, the third passive element 203 may be located on the first side of the first passive element 201, and the semiconductor chip 300 may be located on a third side of the first passive element 201.

By forming a first sub-region R2 a-1, a fifth sub-region R2 e-1, and a sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the third flux layer 273. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming a second sub-region R2 b-1, a seventh sub-region R2 g-1, and an eighth sub-region R2 h-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the second side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming a third sub-region R2 c-1, a fifth sub-region R2 e-1, and a seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the third side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from contaminating the bump pad 124 a-1 (refer to FIG. 1A) under the semiconductor chip 300 positioned on the third side of the first passive element 201.

FIG. 14 is a plan view showing a semiconductor package 1000 m according to an embodiment. Hereinafter, differences between the semiconductor package 1000 l shown in FIG. 13 and the semiconductor package 1000 m shown in FIG. 14 are described.

Referring to FIG. 14 , the semiconductor package 1000 m may further include a fourth passive element 204 on the package substrate 100, a fourth passive element connecting member 254 connecting the fourth passive element 204 to the package substrate 100, and a fourth flux layer 274 adjacent to the fourth passive element 204 on the package substrate 100. The second passive element 202 may be located on the second side of the first passive element 201, the third passive element 203 may be located on the first side of the first passive element 201, and the fourth passive element 204 may be located on the third side of the second passive element 202.

By forming a first sub-region R2 a-1, a fifth sub-region R2 e-1, and a sixth sub-region R2 f-1 of the first passive element adjacent region R2 relatively flat, the flow of the first flux layer 271 to the first side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the third flux layer 273. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming a second sub-region R2 b-1, a seventh sub-region R2 g-1, and an eighth sub-region R2 h-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to the second side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the second flux layer 272. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

By forming a third sub-region R2 c-1, a fifth sub-region R2 e-1, and a seventh sub-region R2 g-1 of the first passive element adjacent region R2 to be relatively flat, the flow of the first flux layer 271 to a third side of the first passive element 201 may be reduced. Accordingly, the first flux layer 271 may be prevented from meeting the fourth flux layer 274. Therefore, an increase in the concentration of the flux mixed with the sealing portion 400 (refer to FIG. 1A) may be prevented. Accordingly, it is possible to prevent delamination between the sealing portion 400 (refer to FIG. 1A) and the package substrate 100.

FIG. 15 is a cross-sectional view illustrating a semiconductor package 1000 n according to an embodiment. Hereinafter, differences between the semiconductor packages 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 n shown in FIG. 15 are described.

Referring to FIG. 15 , the semiconductor package 1000 n may include a wire 370 instead of the chip bump 350. Also, the package substrate 100 may include a wire pad 124 a-3 instead of the bump pad 124 a-1. The wire 370 may connect the semiconductor chip 300 to the wire pad 124 a-3 of the package substrate 100.

By forming the remaining region R3 to be relatively flat, the flow of a flux layer 270 onto the remaining region R3 may be reduced. Accordingly, the flux layer 270 may be prevented from contaminating the wire pads 124 a-3.

FIG. 16 is a cross-sectional view illustrating a semiconductor package 1000 o according to an embodiment; Hereinafter, differences between the semiconductor package 1000 k shown in FIG. 1A to 12 and the semiconductor package 1000 o shown in FIG. 16 are described.

Referring to FIG. 16 , the flux layer 270 may not be present on the passive element region R1 and the passive element adjacent region R2. For example, after the passive element 200 is mounted on the package substrate 100, the flux layer 270 may be removed. For example, when the flux layer 270 includes an aqueous flux, the flux layer 270 may be removed using water.

FIG. 17 is a cross-sectional view illustrating a semiconductor package 1000 p according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 p shown in FIG. 17 are described.

Referring to FIG. 17 , the semiconductor package 1000 p may further include a chip flux layer 370-1. When the semiconductor chip 300 is mounted on the package substrate 100, the chip flux layer 370-1 around the chip bump 350 is generally used. After the semiconductor chip 300 is mounted on the package substrate 100, the chip flux layer 370-1 may be removed. For example, when the chip flux layer 370-1 includes an aqueous flux, the chip flux layer 370-1 may be removed using water. However, in another embodiment, as shown in FIG. 17 , the chip plus layer 370-1 may remain without being removed.

FIG. 18 is a cross-sectional view illustrating a semiconductor package 1000 q according to an embodiment. Hereinafter, differences between the semiconductor package 1000 shown in FIGS. 1A to 1C and the semiconductor package 1000 q shown in FIG. 18 are described.

Referring to FIG. 18 , the semiconductor package 1000 q may include the first semiconductor chip 301 and the second semiconductor chip 302 on the package substrate 100 instead of the semiconductor chip 300. In some embodiments, the first semiconductor chip 301 may be a memory controller chip, and the second semiconductor chip 302 may be a memory chip, e.g., a flash memory chip. The first semiconductor chip 301 may be connected to the bump pads 124 a-1 of the package substrate 100 using the chip bumps 350. The package substrate 100 may further include the wire pads 124 a-3 on the fifth insulating layer 121 e. The semiconductor package 1000 q may further include the wire 370 connecting the second semiconductor chip 302 to the wire pad 124 a-3 of the package substrate 100.

Although FIG. 18 illustrates that the semiconductor package 1000 q includes two semiconductor chips, e.g., the first semiconductor chip 301 and the second semiconductor chip 302, the number of semiconductor chips included in the semiconductor package 1000 q is not limited to two. For example, the semiconductor package 1000 q may include a plurality of second semiconductor chips 302. The plurality of second semiconductor chips 302 may be a plurality of flash memory chips. The plurality of second semiconductor chips 302 may be stacked on the package substrate 100. Additionally, or alternatively, the semiconductor package 1000 q may further include a third semiconductor chip, e.g., a DRAM chip, located on, e.g., the package substrate 100, the first semiconductor chip 301, or the second semiconductor chip 302.

By forming the first semiconductor chip 301 and the second semiconductor chip 302 on the remaining region R3 having a relatively flat upper surface, the flux layer 270 may be prevented from contaminating the bump pad 124 a-1 and the wire pad 124 a-3. Further, a flux layer used to mount the first semiconductor chip 301 on the package substrate 100 may be prevented from contaminating the wire pads 124 a-3.

FIG. 19 is a cross-sectional view illustrating a semiconductor package 1000 r according to an embodiment. Hereinafter, differences between the semiconductor package 1000 q shown in FIG. 18 and the semiconductor package 1000 r shown in FIG. 19 are described.

Referring to FIG. 19 , the second semiconductor chip 302 may be stacked on the first semiconductor chip 301. Although FIG. 19 illustrates that the semiconductor package 1000 r includes two semiconductor chips, e.g., the first semiconductor chip 301 and the second semiconductor chip 302, the number of semiconductor chips included in the semiconductor package 1000 r is not limited to two. For example, the semiconductor package 1000 r may include a plurality of second semiconductor chips 302. The plurality of second semiconductor chips 302 may be a plurality of flash memory chips. The plurality of second semiconductor chips 302 may be stacked on the first semiconductor chip 301. Additionally, or alternatively, the semiconductor package 1000 q may further include a third semiconductor chip, e.g., a DRAM chip, positioned between the first semiconductor chip 301 and the second semiconductor chip 302 or on the second semiconductor chip 302.

FIG. 20A is a cross-sectional view illustrating a semiconductor package 1000 s according to an embodiment. FIG. 20B is an enlarged view of region B2 of FIG. 20A. Hereinafter, differences between the semiconductor package 1000 n shown in FIG. 15 and the semiconductor package 1000 s shown in FIGS. 20A and 20B are described.

Referring to FIGS. 20A and 20B, the semiconductor package 1000 s may include a wire pad adjacent region R-1 adjacent to the wire pad 124 a-3 and a remaining region R-2. The semiconductor chip 300 may be located on the remaining region R-2. The roughness of the upper surface of the wire pad adjacent region R-1 may be less than the roughness of the upper surface of the remaining region R-2. Accordingly, the flux layer 270 may be prevented from flowing into the wire pad adjacent region R-1 and contaminating the wire pad 124 a-3.

FIG. 21 is a flowchart illustrating a method 2000 of manufacturing a semiconductor package according to an embodiment.

Referring to FIGS. 21 and 1A to 1C, the package substrate 100 may be roughened in operation S2100. Through the operation S2100, the roughness of the upper surface of at least one of the first sub-regions R2 a to R2 d may be greater than the roughness of the upper surface of a remaining region R3.

For example, a mask may be arranged on a region of the package substrate 100 that should be relatively flat, and the region of the package substrate 100 that should be relatively rough may be etched. For etching, dry etching, wet etching, or a combination thereof may be used. For example, plasma etching may be used. For example, a mask may be arranged on the remaining region R3, and the passive element region R1 and the passive element adjacent region R2 may be etched. The etched passive element region R1 and passive element adjacent region R2 may be relatively rough, and a non-etched remaining region R3 may be relatively flat. Alternatively, a mask may be arranged on the remaining region R3 and the passive element region R1, and the passive element adjacent region R2 may be etched. As shown in FIG. 2 , the etched passive adjacent region R2 may be relatively rough, and the non-etched remaining region R3 and passive element region R1 may be relatively flat. Alternatively, referring to FIGS. 20A and 20B, a mask may be arranged on the wire pad adjacent region R-1, and the remaining region R-2 may be etched. The etched remaining region R-2 may be relatively rough, and a non-etched wire pad adjacent region R-1 may be relatively flat.

Additionally, a mask may be arranged on a region of the package substrate 100 that should be relatively rough, and the region of the package substrate 100 that should be relatively flat may be further etched. However, by adjusting the etching conditions, e.g., time, concentration, power, flow rate, pressure, temperature, etc., the etching may be performed weaker than the first etching. For example, a mask may be arranged on the passive element region R1 and the passive element region R2, and the remaining region R3 may be lightly etched. Alternatively, a mask may be arranged on the passive element region R2, and the passive element region R1 and the remaining region R3 may be lightly etched. Alternatively, a mask may be arranged on the remaining region R-2, and the wire pad adjacent region R-1 may be lightly etched.

Next, the passive element 200 may be mounted on the passive element region R1 of the package substrate 100 in operation S2200. A solder paste may be used to mount the passive element 200 on the passive element region R1 of the package substrate 100. The passive element connecting member 250 and the flux layer 270 may be formed of the solder paste. The flux layer 270 may not be removed as shown in FIG. 1A or may be removed as shown in FIG. 16 .

Next, the semiconductor chip 300 is mounted on the remaining region R3 of the package substrate 100 in operation S2300. Solder balls and flux may be used to mount the semiconductor chip 300 on the remaining region R3 of the package substrate 100. The chip bump 350 may be formed of the solder ball. The flux may be removed as shown in FIG. 1A, or may not be removed as shown in FIG. 17 . As shown in FIG. 15 , alternatively, the semiconductor chip 300 may be connected to the remaining region R3 of the package substrate 100 using the wire 370.

Next, the sealing portion 400 covering the package substrate 100, the passive element 200, and the semiconductor chip 300 may be formed in operation S2400. Finally, the external connection terminal 500 may be attached by attaching a solder ball to the lower surface of the package substrate 100 in operation S2500.

By way of summation and review, when a flux layer on a package substrate is mixed with a sealing portion, delamination may occur between the package substrate and the sealing portion. In addition, the flux layer may contaminate a bump pad of the package substrate and a chip bump or a wire pad of the package substrate.

In contrast, embodiments provide a semiconductor package for preventing delamination between a package substrate and a sealing portion and preventing contamination of a bump pad or a wire pad by a flux layer. That is, the roughness of the upper surface of the region adjacent to the passive element may be greater than the roughness of the upper surface of the remaining regions, thereby allowing the flux layer to spread more widely over the relatively rough surface. Accordingly, the concentration of the flux layer mixed in the sealing portion can be reduced and delamination between the package substrate and the sealing portion may be minimized. Also, because the upper surface of the remaining region is relatively flat, it may be difficult for the flux layer to flow into the remaining region, thereby preventing the flux layer from contaminating the bump pad or the wire pad.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. 

What is claimed is:
 1. A semiconductor package, comprising: a package substrate including a passive element region, a peripheral region adjacent to the passive element region, and a remaining region; a first passive element on an upper surface of the passive element region; a first semiconductor chip on an upper surface of the remaining region; and a sealing portion covering the package substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side of the first passive element, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side of the first passive element, and wherein a roughness of an upper surface of at least one of the first sub-region to the fourth sub-region is greater than a roughness of the upper surface of the remaining region.
 2. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of the passive element region is greater than the roughness of the upper surface of the remaining region.
 3. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of the passive element region is less than the roughness of the upper surface of the at least one of the first sub-region to the fourth sub-region.
 4. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of the first sub-region is less than the roughness of the upper surface of each of the second sub-region to the fourth sub-region.
 5. The semiconductor package as claimed in claim 4, wherein the first semiconductor chip is positioned on the first side of the first passive element.
 6. The semiconductor package as claimed in claim 4, further comprising a second passive element positioned on the first side of the first passive element.
 7. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of each of the first sub-region and the third sub-region are less than the roughness of the upper surface of each of the second sub-region and the fourth sub-region.
 8. The semiconductor package as claimed in claim 7, wherein: the first semiconductor chip is positioned on one of the first side and the third side of the first passive element, and a second passive element or a second semiconductor chip is positioned on the other of the first side and the third side of the first passive element.
 9. The semiconductor package as claimed in claim 7, further comprising a second passive element and a third passive element respectively positioned on the first side and the third side of the first passive element.
 10. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of each of the first sub-region and the second sub-region is less than the roughness of the upper surface of each of the third sub-region and the fourth sub-region.
 11. The semiconductor package as claimed in claim 10, wherein: the first semiconductor chip is positioned on one of the first side and the second side of the first passive element, and a second passive element or a second semiconductor chip is positioned on the other one of the first side and the second side of the first passive element.
 12. The semiconductor package as claimed in claim 10, further comprising a second passive element and a third passive element respectively positioned on the first side and the second side of the first passive element.
 13. The semiconductor package as claimed in claim 1, wherein the roughness of the upper surface of each of the first sub-region, the second sub-region, and the third sub-region is less than the roughness of the upper surface of the fourth sub-region.
 14. The semiconductor package as claimed in claim 13, wherein the first semiconductor chip is on one of the first side, the second side, and the third side of the first passive element.
 15. The semiconductor package as claimed in claim 14, further comprising: a second semiconductor chip and a third semiconductor chip respectively positioned on the other two sides of the first side, the second side, and the third side of the first passive element, a second semiconductor chip and a second passive element respectively positioned on the other two sides of the first side, the second side, and the third side of the first passive element, or a second passive element and a third passive element respectively positioned on the other two sides of the first side, the second side, and the third side of the first passive element.
 16. The semiconductor package as claimed in claim 13, wherein a second passive element, a third passive element, and a fourth passive element are respectively positioned on the first side, the second side, and the third side of the first passive element.
 17. A semiconductor package, comprising: a package substrate including a wire pad, a peripheral region adjacent to the wire pad, and a remaining region; a passive element on an upper surface of the remaining region; a semiconductor chip on the upper surface of the remaining region; a wire electrically connecting the semiconductor chip to the wire pad; and a sealing portion covering the package substrate, the passive element, the semiconductor chip, and the wire, wherein a roughness of an upper surface of the peripheral region is less than a roughness of the upper surface of the remaining region.
 18. A semiconductor package, comprising: a package substrate including a passive element region, a peripheral region adjacent to the passive element region, and a remaining region; a plurality of external connection terminals on a lower surface of the package substrate; a passive element on an upper surface of the passive element region; a memory controller chip on an upper surface of the remaining region; a chip bump connecting the memory controller chip to the package substrate; a memory chip on the memory controller chip or the remaining region; a wire connecting the memory chip to the package substrate; and a sealing portion covering the package substrate, the passive element, the memory controller chip, the chip bump, the memory chip, and the wire, wherein the peripheral region includes a first sub-region on a first side of the passive element, a second sub-region on a second side opposite the first side of the passive element, a third sub-region on a third side of the passive element, and a fourth sub-region on a fourth side opposite the third side of the passive element, and wherein a roughness of an upper surface of at least one of the first sub-region to the fourth sub-region is greater than a roughness of the upper surface of the remaining region.
 19. The semiconductor package as claimed in claim 18, wherein a width of the at least one of the first sub-region to the fourth sub-region along a direction perpendicular to a thickness direction of the package substrate is about 10 µm to about 500 µm.
 20. The semiconductor package as claimed in claim 18, wherein a difference between the roughness of the upper surface of the at least one of the first sub-region to the fourth sub-region and the roughness of the upper surface of the remaining regions is 80 nm or more. 